Conventional device structures for a field effect transistor (FET) fabricated using complementary metal-oxide-semiconductor (CMOS) process technologies include a semiconductor layer, a source and a drain defined in the semiconductor layer, a channel defined in the semiconductor layer between the source and drain, and a control gate electrode. The material constituting the gate electrode in such conventional planar device structures contains polycrystalline silicon (polysilicon) or a metal applied by an additive process that involves blanket deposition of the material and patterning with a conventional lithography and etching process. When a control voltage exceeding a characteristic threshold voltage is applied to the control gate electrode, an inversion or depletion layer is formed in the channel by the resultant electric field and carrier flow occurs in the depletion layer between the source and drain (i.e., the device output current).
Non-volatile random access memory (NVRAM) refers generally any type of random access memory that retains the stored binary data even when not powered. A conventional device structure used as a memory cell in a NVRAM modifies a standard FET to add an electrically isolated or floating gate electrode that affects conduction between the source and drain. A tunnel dielectric layer is interposed between the floating gate electrode and the channel. The control gate electrode is separated from the floating gate electrode by an intergate dielectric layer.
Improved fabrication methods are needed for the memory cells of a NVRAM that permit the use of high operating voltages and that simplify device fabrication using CMOS technology.